In certain integrated circuits (ICs), such as those based on System-On-a-Chip (SOC) technology, various semiconductor devices having various functionalities are formed on a single chip in order to satisfy the requirements and needs of the end use products. When these semiconductor devices operate at different voltages, the fabrication of the integrated circuit typically requires the formation of dielectric layers having varying thicknesses and compositions. For example, high voltage power transistors, such as those used to program EEPROM devices, typically require thicker gate oxides than the lower voltage transistors associated with memory storage in DRAM circuitry.
Various approaches have been developed in the art for forming gate oxide layers having different thicknesses as required to accommodate the particular voltage requirements of different devices present on the same integrated circuit. Such multi gate oxide structures, which may include triple gate oxide (TGO) structures and quadruple gate oxide (QGO) structures, may be achieved, for example, by using a separate process to provide each of the gate oxide thicknesses required by the various devices in the integrated circuit.
Alternately, gate oxide layers having different thicknesses may be formed by dividing a chip into multiple regions, and then providing each region with a specific gate oxide thickness. For instance, it is possible to form a chip such that it is divided into three separate regions with associated gate oxide layers having thicknesses suitable for high voltage, low voltage and medium voltage devices. Accordingly, it is required that the multi gate oxide layer formation technology that is used to fabricate such devices is capable of producing gate oxide layers of varying thicknesses as required to accommodate the needs of a particular device.
Despite the development of the aforementioned processes for forming gate oxide layers having different thicknesses in the same integrated circuit, these processes suffer from some notable infirmities. In particular, the performance characteristics of devices manufactured by these processes are frequently less than optimal. Often, these characteristics are particularly poor in the core devices.
There is thus a need in the art for a multi gate oxide process, and for products manufactured by this process, that overcome this infirmity. In particular, there is a need in the art for a method for manufacturing multi gate oxide devices in which the performance characteristics of the core devices are comparable to the devices disposed elsewhere in the integrated circuit. These and other needs are met by the methodologies and devices described herein.